Q:

Which of the following condition is true for determining overflow condition in 2’s complement?

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Which of the following condition is true for determining overflow condition in 2’s complement?


  1. When adding two positive numbers gives a negative result or when two negatives give a positive result.
  2. If sign bit (MSB) of result and sign bit of two operands are of different signs.
  3. The ‘1’ in the MSB position indicates a negative number after adding two positive numbers.
  4. All of the above

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 (d).All of the above

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COMPUTER ARCHITECTURE - DIGITAL DATA REPRESENTATION MCQ

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