Q:

Number of gates for the full adder can be reduced if JK flip-flop is used for

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Number of gates for the full adder can be reduced if JK flip-flop is used for


  1. storing the carry
  2. subtracting the carry
  3. both a and b
  4. None

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 (a).storing the carry

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DIGITAL LOGIC DESIGN - DLD LAB EQUIPMENT AND EXPERIMENTS MCQ

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