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There are________________ basic types of flip-flop based on clock trigger
The characteristic equation of any flip-flop describes the __________________ of the next state in terms of the present state and inputs
The normal data inputs to a flip-flop (D, S and R, J and K, T) are referred to as ________________ inputs
Asynchronous inputs, just like synchronous inputs, can be engineered to be ______________
___________ and Clear should not be 0 at the same time; otherwise, both the outputs will be 1, which is known as invalid state
Which table indicates the input conditions of the flip-flops necessary to cause all possible next state transitions of a flip-flop?
When a circuit is self- correcting?
A PLA consists of two-level____________ circuits on a single chip
In which of the following types of counters, the flip-flops do not change states at exactly the same time?
The number of states through which the counter goes is also known as ____________
It contains an equal resistor or current source segment for each possible value of DAC output
The total current can be converted into the corresponding voltage by using a/an _______________
The number of resistors required for an N-bit DAC is 2N in the case of _____________
The characteristics of a DAC, which are generally specified by the manufacturers
To start the conversion in successive approximation DAC the programmer sets the MSB to ___________ and all other bits to __________
The major block(s) of the dual- slope ADC
A counter with 10 states
In asynchronous flip-flop, ______________ and clear pin shows negation
It is a single input version of J-K flip-flop formed by tying both the inputs of J-K
In flip-flop, the ___________ arrow shows positive transition on the clock
total questions: 119

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