COMPUTER ARCHITECTURE - DIGITAL COMPONENTS MCQ

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The number of control lines for 32 to 1 multiplexer is
The logic 0 level of a CMOS logic device is approximately
How many select lines will a 32:1 multiplexer will have
Which of following consume minimum power?
ABCD - seven segment decoder / driver in connected to an LED display. Which segments are illuminated for the input code DCBA = 0001
How many flip-flops are required to produce a divide-by-32 device?
A demultiplexer can be used as
'n' Flip flops will divide the clock frequency by a factor of
If the clock input applied to a cascaded Mod-6 & Mod-4 counter is 48KHz. Than the output of the cascaded arrangement shall be of
Logic gates with a set of input and outputs is arrangement of
A flip-flop is a binary cell capable of storing information of
A device/circuit that goes through a predefined sequence of states upon the application of input pulses is called
A combinational logic circuit which sends data coming from a single source to two or more separate destinations is
Advantage of synchronous sequential circuits over asynchronous ones is
A basic AND gate consists of ______________inputs and an output
In the AND gate, the output is ‘High’ or gate is ‘On’ only if both the inputs are ______________
It is a simple combinational digital circuit built from logic gates
It is used to subtract two inputs having more than one bit
It is a circuit, which subtracts two inputs each of one bit
It is the converse of decoding and contains 2^n (or fewer) input lines and n output lines

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