Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line…??

COMPUTER ARCHITECTURE - INPUT OUTPUT ORGANIZATION MCQ

• In memory-mapped I/O…
• The usual BUS structure used to connect the I/O devices is
• The advantage of I/O mapped devices to memory mapped is
• The system is notified of a read or write operation by
• To overcome the lag in the operating speeds of the I/O device and the processor we use
• The method of accessing the I/O devices by repeatedly checking the status flags is
• The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is
• The method which offers higher speeds of I/O transfers is
• The process where in the processor constantly checks the status flags is called as
• The interrupt-request line is a part of the
• The return address from the interrupt-service routine is stored on the
• The signal sent to the device from the processor to the device after recieving an interrupt is
• When the process is returned after an interrupt service ______ should be loaded again
• The time between the receive of an interrupt and its service is ______
• Interrupts form an important part of _____ systems
• ______ type circuits are generally used for interrupt service lines
• The resistor which is attached to the service line is called _____
• An interrupt that can be temporarily ignored is
• The 8085 microprocessor respond to the presence of an interrupt
• CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged
• Which interrupt is unmaskable…??
• From amongst the following given scenarios determine the right one to justify interrupt mode of data transfer
• How can the processor ignore other interrupts when it is servicing one
• When dealing with multiple device interrupts , which mechanism is easy to implement
• The interrupt servicing mechanism in which the reqesting device identifies itself to the processor to be serviced is
• Which table handle stores the addresses of the interrupt handling sub-routines
• Interrupts initiated by an instruction is called as
• The anded output of the bits of the interrupt register and the mask register are set as input of:
• ____ register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt
• ______ interrupt method uses register whose bits are set separately by interrupt signal for each device:
• In daisy chaining device 0 will pass the signal only if it has
• _________ method is used to establish priority by serially connecting all devices that request an interrupt
• Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line…??
• The processor indicates to the devices that it is ready to recieve interrupts
• The starting address sent by the device in vectored interrupt is called as
• The code sent by the device in vectored interrupt is _____ long
• In vectored interrupts, how does the device identify itself to the processor..?
• DMA interface unit eliminates the need to use CPU registers to transfer data from
• The average time required to reach a storage location in memory and obtain its contents is called the
• The process that periodically checks the status of an I/O devices, is known as
• A bus connecting processor and memory, is known as
• 1000 disks having 1,200,000-hour MTTF and disks being used 24 hours a day, and failed disks are being replaced with a new ones, then no that will fail over five years (43,800 hours) is,
• A unit on the bus that initiates bus requests is called
• Request, which is used for indicating a read request for memory, is known as
• Reads/writes requests to I/O devices, are called
• The average time for reading/writing the 512-byte sector for the disk rotating at 10,000 RPM when its time is 6 ms, its transfer rate is 50 MB/sec, and its controller overhead is 0.2 ms
• 1GB of data is referred in bytes as
• A bus which is designed for allowing processors, I/O devices and memory, is called a
• When the disks rotate at 5400 RPM-15,000 RPM, then they have average rotational latency is between
• The 32-bit, 33MHz PCI bus will have peak bandwidth of about
• Spread of data in the multiple disks, is refered to as
• The data transfer rate is given by the formula
• Measuring the continuous service accomplishment and equivalently of the time to failure from a reference point is called
• The higher availability cost is reduced to 1/N, where N is the
• A scheme in which portions of the I/O address space are given to I/O devices, is called
• To improve the availability of storage of disk, leveraging redundancy is captured in the
• The hardware component replacing while the system is being run, is known as
• For accessing data, the operating system must direct the disk using three-stage process called
• The peak rate which transfer data between the I/O device and the main-memory, is known as

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