Noise margin is calculated with the difference of

DIGITAL LOGIC DESIGN - DIGITAL INTEGRATED CIRCUITS MCQ

• Common emitter transistors are
• The maximum number of inputs connected to the gate is called
• CMOS stands for
• Exceeding the maximum load on circuit causes
• Bipolar are constructed with
• Delay is measured with the unit
• No current flow in transistor is called
• The behavior of a positive logical NAND gate in terms of low input produces a
• DTL stands for
• 1ns is the value equal to
• Voltage between Vcc and Voh is referred as
• Unwanted signals in image is called
• ECL stands for
• MOS stands for
• RTL stands for
• A standard TTL NAND gate uses a supply voltage of
• 0 in the logic circuit represents
• FET transistors are
• Emitter current is given by
• Term being used for loading is
• Unit of noise margin is
• TTL digital logic family uses
• CMOS digital logic family uses
• Bipolar Junction Transistor (BJT) can be either
• Basic building block of digital circuit is/are
• Bipolar transistors work on
• BJT stands for
• TTL stands for
• IC stands for
• Power formula is
• MOSFET is also called
• All high nputs of NAND gate produces
• Standard parameter value of Vol in noise margin is
• FET stands for
• Unit used for power dissipation is
• Standard parameter value of Vih in noise margin is
• Low input of NAND produces output as
• Standard parameter value of Voh in noise margin is
• For proper operation gate requires
• Maximum noise is referred to as
• 1 in the logic circuit represents
• Vol represents the
• Modification of DTL is
• Standard value of Vil in noise margin is
• MOS is being used in
• Noise margin is calculated with the difference of
• Fan-out is calculated from the ratio of
• Any high input of NOR produces output as
• The First digital Integrated circuits family that was introduced commercially is
• Forward biased transistor has voltage greater than

This question belongs to these collections

• DIGITAL LOGIC DESIGN - DIGITAL INTEGRATED CIRCUITS MCQ

Similar questions